2024年3月29日 · "These units will supports processing most AVX-512 instructions in a single cycle, whereas Zen 4 has 256-bit units" " The widening of the SIMD unit width to 512 bits alone means that the theoretical compute performance given in FLOPS (but the same applies to ops working on integer data types) is doubled.

2023年5月3日 · AMD Announces Ryzen 9950X, 9900X, 9700X, & 9600X Zen 5 CPUs, Extends AM5 Life, & AI CPUs youtu. upvotes ...

2022年8月10日 · The zen 1/3 team is the "new build" team and the Zen 2/4 team are the more incremental team. It's possible this means that Zen4 has more in common with Zen2 because it was being developed ahead of Zen3, based on Zen2.

2022年6月7日 · Obviously zen 4 is going to be 40%+ faster in multi-thread. 5800X3D is slower than the 5800X even in that regard. Zen 4 has a doubled L2. AMD"s L2 cache is 10 times faster than it's L3. Great that the 5800X3D has a doubled L3 but having a larger L2 is just vastly superior given the speed difference. On top of that Zen 4 also has a much higher ...

2023年2月8日 · Yes. My RAM doesn't have EXPO, but in my fight to get >6000, I have learnt to manually set everything. It just baffles me that it can run 6000-28-35-35 and everything else as tight as Hynix can go at 1.4V, but no matter how relaxed timings, what volts and termination resistances, it won't budge.

2022年9月10日 · So for Zen 4 the ratio is 2:3:3 (FCLK:UCLK:MEMCLK). Some test examples from Zen 3: DDR4-2400 with a 1:1:1 ratio nets you 34.25GB/s mem bw. DDR4-3200 with a 3:2:4 ratio (1200:800:1600) nets you 45.79GB/s mem bandwidth. That's pretty much exactly the 33% increase to memory bandwidth you would expect from DDR4-2400 up to DDR4-3200.

2023年11月22日 · On Zen 2 and Zen 3, running UCLK and FCLK at the same frequency reduces memory latency by a significant number of clock cycles. The goal is generally to run at the highest possible UCLK and FCLK (whichever caps out lower is the limit). On Zen 4, running UCLK and FCLK at the same frequency provides no memory latency reduction.

Running uclk=memclk/2 for max memclk is a borderline advantage at best, so if you don't have optimal circumstances it's just not worth the bother. A uclk=memclk setup with ~6000-6200mt/s, max fclk and tuned timings will be basically as good - at least on Zen 4 Raphael parts.

2022年10月2日 · On Zen 3 and Zen 2, decoupling the FCLK from the UCLK/MCLK caused a latency penalty. On Zen 4, it’s no longer an issue (and actually necessary to hit the speeds DDR5 excels in because the FCLK cannot hit frequencies as high as the theoretical maximum of DDR5). So leaving that at auto iirc defaults to a 2000 MHz FCLK.

It can go as low as 4x tRRDS (so unless they mistyped, 16 doesn't really do much here) 4-4-16 for RRDS/RRDL/FAW is pretty typical for B-die. Edit : so apparently Zen 4 cannot go below 20, but on AM4 16 is pretty much the optimal value.