In this paper, we will present a holistic approach for 6T-SRAM designs using gate-all-around (GAA) transistors, which will firmly address process integrations and circuit aspects arising at the 5nm node.

In this article, we propose a carbon nanotube (CNT) field-effect transistor (CNFET)-based static random access memory (SRAM) design at the 5-nm technology node

SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the /spl beta/ ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs ...

2024年6月21日 · We have analysed and compared the signal stability, power consumption and speed performance of static random-access memory (SRAM) circuits based on Si FETs and 2DMFETs across different technology...

This workshop presents a basic overview of different SRAM Cell Designs using LTSpice and ASU's Arizona State Predictive PDK (ASAP) 14nm FinFET node, using an intuitive approach to designing a simple SRAM Cells. This workshop also provides deep insights into recent advancements and current research trends in Memory Cell Designs.

2022年3月16日 · So, in this paper, a comprehensive review of pre-existing SRAM cell configurations for seven transistor (7T) is presented. Each cell is designed at 32 nm technology node using CMOS Predictive Technology models with the aspect ratios reported in their respective papers.

2025年3月26日 · Abstract page for arXiv paper 2503.19544: Design of Energy-Efficient Cross-coupled Differential Photonic-SRAM (pSRAM) Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems ... (0.03 pJ) per bit and a footprint of 330x290 um^2 using the GlobalFoundries 45SPCLO process node. These bitcells …

2021年8月1日 · FinFETs are promising emerging devices, which can improve the performance of SRAM designs at lower technology nodes. This review paper presents different types of SRAM bitcells and memory system architectures. It also discusses the detailed analysis of SRAM bitcells based on various highly explored FinFET devices in sub-10nm domain.

2020年1月1日 · This paper demonstrated CMOS based 6T SRAM cell design and the results are compared for different technology nodes (180 nm, 90 nm, 65 nm, 45 nm). It is demonstrated that BSIM3 CMOS based 6T SRAM offers less delay, less read margin and less write margin resulting in improved stability of the cell as compared to previously reported data.

Abstract: SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are necessary to continue with technology scaling. Nanosheet (NSH) technology improves SRAM cell write-ability by having 50 mV more write trip point (WTP) than FinFET (FF) SRAM due to reduced bit line (BL) resistance (due to wider metal CD) and ...