2024年1月9日 · You need modify drivers/clk/imx/clk-fracn-gppll.c to support new pixel clock Please refer 74.2.3 Clock configuration in RM. If we add a frequency of 537.6MHz(Pixel clock *4), then MFI=112, MFN=0, MFD=1, rdiv=0, odiv=5

2024年9月23日 · One of the existing values in the imx_fracn_gppll_rate_table is 10x. I tried to use that, by setting my clock rates in the device tree to the following: assigned-clock-rates = <650000000>, <65000000>, <400000000>, <133333333>;

I'm trying to use the ilitek ili9881c driver with specific configurations to get the panel to display correctly, but I have been unsuccessful so far. I do some displays with Weston and modetest. In 2 cas, The panel displays something initially, but then the screen becomes blurry and eventually becomes completely unreadable.

2025年2月10日 · ana_mfn = readl_relaxed(pll->base + PLL_STATUS); ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn); return 0;

System Manager firmware for i.MX processors. Contribute to nxp-imx/imx-sm development by creating an account on GitHub.

The strategy to get to the PLL setting for a rate is: - The rate table is searched for suitable rates, so for standard rates the same settings are used as without this patch - Then try to only adjust mfn, on fractional PLLs only, which specifies the fractional part of the PLL.

- Cast result of 'parent_rate * mfn / mfd' to unsigned long instead of u32. - Clarify how this issue was discovered in the commit message. - Rebased on Linux 4.8. Changes since v1: - Use correct subsystem name in commit summary. - Use 'Fixes:' tag to indicate bug fix. - Revise argument for choosing the denominator register value after

MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This is a just sign bit. This patch makes different calculation for i.MX27. Signed-off-by: Alexander Shiyan <[email protected]>--- arch/arm/mach-imx/clk-pllv1.c | 23 +++++---- 1 file changed, 19 insertions(+), 4 deletions(-)

Hi, Alexander Shiyan writes: > MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This > is a just sign bit.

u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); u32 div = readl_relaxed(pll->base) & pll->div_mask; + u64 temp64 = (u64)parent_rate; - return (parent_rate * div) + ((parent_rate / mfd) * mfn); + temp64 *= mfn; + do_div(temp64, mfd); + + return (parent_rate * div) + (u32)temp64;}