• YARC provides fault tolerance by using a unique routing ta-ble structure to configure the network to avoid bad links and nodes. YARC also provides link-level retry and automati-1YARC stands for ’Yet Another Router Chip’, and is also Cray spelled backwards.

6.5.1 Cray YARC Router. 该芯片基于Hierachical Croassbar方案，但略有不同，其结构如下图。整个router被分割为64个tile，每个tile包含一个8*8的switch及一个input port和output port、并对应input buffer、row buffer以及column buffer。tile之间的通信通过row bus和column channel。

YARC is divided into a 8 × 8 array of tiles where each tile. This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor.

We propose an optical switch architecture that exploits high-speed optical interconnects to build a flat crossbar with multiple-writer, single-reader links. Unlike YARC, which uses small buffers at various stages, the proposed design buffers only at input and output ports.

This thesis presents a hierarchical router organization that results in a distributed, complexity-effective microarchitecture and maintains high performance. As a case study, the implementation of this microarchitecture in the Cray YARC router with 64 ports will also be presented.

This paper discusses the network used in the Cray X2 (BlackWidow) supercomputer. There are actually two different networks: the system-level network that connects processors together and the router-level on-chip network that implements a single-chip high-radix router (YARC). What topology, routing, and flow-control is used in each network?

2020年6月14日 · A tile-based high-radix router architecture, named YARC and widely adapted in CrayXT HPC systems, divides the single large N -port crossbar into N tiles, and shows its capacity to effectively reduce memory overheads by 40% and improve the throughput by 20–60% compared with conventional crossbar implementation [6].

more recent BlackWidow system is built from the Cray YARC router, which provides a total bandwidth of 2.4 Tbps, and is divided into 64 ports. The YARC router uses an 8 " 8 array of tiles (see Figure A).3 Each YARC tile consists of an input and an output port, an 8 " 8 crossbar subswitch providing connectivity between the eight tiles in the row

2012年2月8日 · YARC is an acronym that is short for "Yet Another Router Chip", and it is the architectural name that Cray slapped onto the high radix router at the heart of the experimental "BlackWidow" supercomputer.

For example, Cray’s YARC is a high-radix, high performance, single-chip switch [26], with 768 pins shared by 64 bi-directional ports, giving an aggregate bandwidth of 2.4Tb/s. Each port has three input and three output data signals, but the use of differential signaling, necessary to improve high speed signaling reliability, means that 12 ...