矽鍺（英語： Silicon-germanium ，縮寫為SiGe），是一種合金，依矽和鍺的莫耳比可以表示成Si x Ge 1-x 。 常被用作 積體電路 （IC）中的 半導體材料 ，可做成 异质结双极性晶体管 或 CMOS 電晶體中的應變誘發層（strain-inducing layer）。

2018年1月30日 · Influences of source and drain recess structures on SiGe epitaxy growth, SiGe step height, facet formation, ID,sat and resistance performance are investigated. Growth rate of SiGe height increases with decreased recess width at a fixed depth of 62 nm.

2015年5月31日 · This article reviews the selective epitaxy growth of intrinsic, B- and C-doped SiGe layers on recessed (or flat) exposed Si areas for MOSFETs as well as on Si-fins for FinFETs. A detailed empirical model for the growth, integration issues including epitaxy quality, selectivity, dopant incorporation, and pattern dependency (or loading effect) is ...

In this paper we evaluate a critical defect of “Abnormal epi” seen during the selective epitaxial growth of in-situ boron (B) doped SiGe on FinFETs. Abnormal epi here refers to abnormally large and spurious epitaxial growth defect occurring as random instances on a wafer die.

2003年7月31日 · SiGe (硅锗)技术是最近的一项技术革新，能同时改善接收机的功耗、灵敏度和动态范围。 GST-3是新的基于硅锗技术的高速IC处理工艺，其特点是具有35GHz的特征频率(f T )。

2008年2月15日 · Locally strained Si technology using embedded SiGe has been used to improve pMOSFET device performance through hole mobility enhancement. Embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si pMOSFET source and drain areas.

2002年9月2日 · This application note describes how silicon germanium enhances IC performance in RF applications. A Giacoleto model is used to analyze noise effects. Wider gain bandwidth of SiGe technology is shown to provide lower noise performance. The impact of …

Controlled experiments demonstrate an exponential correlation between the ratio of SiGe lateral width and B% concentration in SiGe film and merged epi defect density, highlighting a potential quality control parameter to reduce merged epi formation and related yield loss.

2016年9月1日 · In this study, the process integration of SiGe selective epitaxy on source/drain regions, for 16/14 nm nodes FinFET with high-k & metal gate has been presented. Selectively grown Si 1 − x Ge x (0.35 ≤ × ≤ 0.40) with boron concentration of 1 × 10 20 cm − 3 was used to elevate the source/drain of the transistors.

2020年2月27日 · 接下来我们将详细阐述 SiGe 薄膜（塑性和弹性（图 2））的弛豫和 SiGe 工艺选择性。 最后，我们将展示高 Ge 含量 SiGe 在不同类型 pMOS 晶体管中的集成：Si FinFET、应变 SiGe 核心 FinFET、应变 SiGe 包层 FET 和应变 Ge FET（图 3）。