We present a new kind of silicon device: a High-Voltage vertical JFET, originally conceived as a candidate for the High-Voltage Multiplexing switch in the ATLAS upgrade of the silicon …

1.结型场效应管的概述（JFET）：结型场效应管基本结构（JFET）： 这里提示一下N沟道和P沟道的图像画法（不要搞混了） 2.结型场效应管的工作原理（以N沟道为例）（JFET）： 注意这 …

2019年3月1日 · Here we report on the design of a custom vertical JFET for HV Mux that is fabricated using only planar silicon technology and therefore promises to be simpler and …

This 200 MHz JFET cascode circuit features low crossmo- dulation, large-signal handling ability, no neutralization, and AGC controlled by biasing the upper cascode JFET.

An advanced low-cost and low-power high-voltage (HV) startup circuit which uses a 50 V pJFET and a 700 V T-nJFET (triple RESURF nJFET) is proposed. Compared with traditional …

This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(threshold voltage) and Idsat, without DIBL effect over full operating Vds …

In this work, a gradient doped integrated HV junction field effect transistor (JFET) for HV start-up circuit with high ON-BV and high I Dsat is proposed. In the resistance region and drift region of …

Both n-type and p-type HV-JFETs have been successfully fabricated in the silicon processing facility of Brookhaven National Laboratory. Probe station measurements of un-irradiated …

By using the available planar technology for the silicon processing, we fabricated in our Clean Room dedicated batches of HV JFETs, first n-type and then p-type channel JFETs. The …

The first CMC (Compact Modeling Council) standard high voltage MOSFET model HiSIM_HV developed by Hiroshima University is explained as well. Finally, characterization and …