2020年1月7日 · Abstract: Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as it relies on a storage cell that …

This letter presents the first GC-eDRAM in 16-nm FinFET technology, featuring a mixed-VT 3T gain-cell structure to minimize the storage node (SN) leakage. The implemented 1-Mbit 3T GC-eDRAM is fully logic-compatible and provides a 2× smaller bitcell size compared to a 6T SRAM with similar design rules, offering the highest density logic ...

2023年6月2日 · GC eDRAM是一种6T SRAM和1T1C eDRAM折中选择的产物，它结合了SRAM (与数字CMOS技术兼容)和1T1C eDRAM (高存储密度)的优点，同时规避了SRAM (单元面积大)和1T1C eDRAM (破坏性读取、回写操作和需要特殊工艺步骤)的缺点。 但是，与SRAM相比，GC eDRAM的主要缺点仍然是其数据保持的动态特性，需要定期进行刷新操作。 最小的2T GC eDRAM电路如图3-18所示，由一个写晶体管 (QW)与一个读晶体管 (QR)组成，其中读晶体管 …

2017年7月7日 · This chapter discusses the basic operation of GC-eDRAM, as well as its many advantages and few drawbacks compared to SRAM and 1T-1C eDRAM. The chapter then provides a detailed review of the state-of-the-art of GC …

在本文中，我们介绍了 gc-edram 建模工具 (gemtoo)，这是第一个估算 gc-edram 时序、内存可用性、带宽和面积的建模工具。 该工具考虑了与技术、电路和内存架构相关的参数，并且能够评估架构转换以及高级晶体管级效应，例如由于存储数据的恶化而导致的访问延迟 ...

As opposed to conventional 1T-1C eDRAM, gain-cell (GC) based eDRAM (GC- eDRAM) is fully compatible with mainstream digital CMOS technologies, since it is built exclusively from MOSFETs and, optionally, the readily available metal

This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to …

2021年11月1日 · We analyze the potential to exploit the low leakage power and compact size of GC-eDRAM in the design of low power embedded systems. We replace the data array in an L1 data cache and in an L2 cache, which are conventionally implemented with SRAM, with a new generation (3T,4T) GC-eDRAM [1], [2], [3].

•The main barrier for GC-eDRAM is its limited DRT, which leads to: • Increased power consumption - • Lower availability •This gets worse with transistor scaling, as the parasitic capacitance is reduced •In addition, DRT is a complex factor, as it is dependent on: • Written voltage levels (V boost, CI/CF) • Read Frequency:

2020年9月28日 · Abstract: Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as two transistors and that can be fabricated without additional process steps.