2005年10月1日 · A new DRAM gate stack of WSi x /WN/polysilicon with a 50 Å WN layer was studied as a gate stack of future technologies. With the 50 Å WN layer inserted between the WSi x and polysilicon, the tungsten silicide etch was able to be very selective to the thin WN layer, and the thickness of the polysilicon underneath can be minimized.

Abstract: Low resistive tungsten (W) interconnects using chemical vapor deposited W (CVD-W) films deposited on B 2 H 6-reduced W nucleation layers have been successfully developed for the buried gate electrode of sub-30nm dynamic random access memory (DRAM). The low resistive W film showed excellent gap fill performance and larger grain size ...

氮化钨 (WN x ) 薄膜通过原子层沉积 (ALD) 在 200-350°C 的温度范围内从乙硼烷 (B 2 H 6 )、六氟化钨 (WF 6 ) 和氨 (NH 3 ) 中生长，用于应用于动态随机存取存储器 (DRAM) 中的接触势垒层。 在本文中，B 2 H 6 用作附加还原剂以制备低电阻率 ALD-WN x 薄膜，其电阻率在 300-410 μΩ cm 范围内，取决于约 10 nm 厚的沉积条件电影。 随着沉积温度的升高，观察到生长速率增加，但在 275 至 300°C 的温度范围内获得了几乎恒定的约 0.28 nm/循环的生长速率。 沉积膜的特性，包 …

In this paper, we present the implementation of W/WN/poly gates in a 135 nm sub-8F2 vertical cell DRAM technology with dual gate oxide planar support transistors. Key features include low sheet resistance wordlines, high performance peripheral logic circuitry and a …

To mitigate the constraint of the increased gate resistance for dual-workfunction-gate (DWG) cell transistors as a standard platform in the DRAM industry, a Middle-silicon- TiN Gate (MSTG), which replaces the n+-polysilicon with an ultra-thin TiN/silicon interlayer/bulk TiN was demonstrated in a fully integrated 1x-nm 16Gb, and provides ...

2012年11月1日 · Self-aligned contact (SAC) failures issues in W-dual poly metal gate of DRAM. Asymmetrical relief of W stress may create torque resulting in gate leaning. Stress induced by transformation of the amorphous WN x barrier and side of the gate. Decreased SAC failure and improved reliability by reducing the NH 3 pre-purge time.

2013年9月1日 · Due to the demand of high-speed/high-density and low power application of memory devices, tungsten dual poly gate (W-DPG; W/barrier metals/n+ and p+ poly-Si) electrode could be a good solution in...

2007年4月24日 · Tungsten dual polygate (W-DPG) stacks with diffusion barriers formed by the Ti (N) process were investigated in terms of gate contact resistance (Rc) and the polydepletion effect. The Ti layer in the Ti/WN diffusion barrier is found to be converted into a TiSi x /TiN bilayer during the postdeposition annealing process.

2008年10月1日 · Novel dual work function (DWF) based transistors featuring low gate resistances are presented. The process discussed enables extremely fast array timings easily and is thus key to fulfilling the performance requirements for high performance DRAM chips.

2005年10月1日 · However, the integration of tungsten alloy in poly-silicon/TiN/W (WN)/high-k gate stack requires new dry etch approaches. This work focuses on plasma etching of W and WN embedded in metal gate...