2016年11月17日 · Abstract: This brief proposes a novel power-gated 9T (PG9T) static random access memory (SRAM) cell that uses a read-decoupled access buffer and power-gating transistors to execute reliable read and write operations.

This study presents a new 9 transistor (9T) static random access memory (SRAM) architecture with effortless and stable read operation. The proposed topology is implemented in predictive technology model (PTM) 16nm technology using LTspice software.

2024年2月1日 · In this work, we propose an IMC macro based on customed 9T-SRAM, which can be configured in memory, Boolean logic and multiply-and-accumulate (MAC) modes. The 9T-SRAM adopts read/write decoupled and a tail transistor structure, which enhances the read stability and reduces power consumption.

2024年3月1日 · In this study, we proposed an IMC macro based on customed 9T-SRAM. The IMC macro can operate in traditional memory mode, Boolean logic mode and MAC mode. The 9T-SRAM adopts read/write decoupled structure, and the …

The presented 9T SRAM cell’s important layout parameters are evaluated using LTSPICE simulations. Comparable findings utilizing conventional 6T (CONV6T), conventional 7T (CONV8T), conventional 8T (CONV8T), conventional 9T (CONV9T), and conventional 10T (CONV10T) SRAM cells are shown with the estimated results.

2019年12月2日 · We present a circuit-level technique of designing a lower write-power along with variability-resistant 9-MOFTET static random-access memory cell. Our proposed bitcell exhibits lower write-power consumption owing to reduction of activity factor and breakup of feedback path between the cross-coupled inverters during write operation.

2023年10月23日 · In this research work, a single-ended 9T (9 Transistor) SRAM cell is proposed. All the cells discussed throughout this study are designed and simulated at 180 nm technology node with a voltage supply of 1V. The proposed cell performs all of its operations (read or write) via a single bitline.

2019年7月18日 · To cater to the requirements of higher robustness and lower hold power dissipation, a transmission gate-based 9T SRAM is proposed, which achieves these requirements at the cost of slightly higher read and write access time. The simulations are performed utilising a 16-nm complementary metal oxide semiconductor model.

2024年2月1日 · This paper presents a reliable single-ended nine-transistor (9T) static random access memory (SRAM) cell which is based on 16 nm graphene nanoribbon FETs (GNRFETs) technology. Single-ended operation significantly reduces switching activity and layout area.

2024年9月13日 · This paper proposes a conflict-free 9T cell, a 9T SRAM cell designed for ultra-low voltage, in order to address the writing problem of the 9T cell based on the 28 nm process. By preventing the charge and discharging of transistors during the writing process, the conflict-free 9T cell improves its efficacy at ultra-low voltages.