TI’s CD74HC107 is a High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset. Find parameters, ordering and quality information.

TI 的 CD74HC107 是一款 具有复位功能的高速 CMOS 逻辑双通道下降沿 J-K 触发器。 查找参数、订购和质量信息.

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input.

The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.

The ’HC107 and CD74HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs.

CD74HC107M由TI (德州仪器)设计生产，立创商城现货销售。 CD74HC107M价格参考￥5.58。 TI (德州仪器) CD74HC107M参数名称：类型：JK-型；触发沿：下降沿；工作电压：2V~6V；时钟频率 (fc)：60MHz；功能：复位；元件数：2；每个元件位数：1；输出类型：互补型；传播延迟 (tpd)：29ns@6V,50pF；系列：74HC系列；灌电流 (IOL)：5.2mA；拉电流 (IOH)：5.2mA；静态电流 (Iq)：4uA；输入电容：10pF；工作温度：-55℃~+125℃。 下载CD74HC107M中文资料 …

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input.

LED原理：P3.0~P3.7 既为LED 的显示段码输出，又为LED 的位选输出，通过F449 的P4.1、P4.2 口控制74HC373 的LE 端来选择来实现输出的有效数据。 其工作方式为： 当P4.1 为高电平，... 元器件型号为74HC107的类别属于半导体分立半导体，它的生产商为NXP (恩智浦)。 厂商的官网为：......点击查看更多.

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input.