Proposed study presents the design and comparative analysis of a 6 T XOR gate implemented in $45 \mathrm{~nm}, 90 \mathrm{~nm}$, and 180 nm CMOS technologies using Cadence tools. The aim is to assess the performance metrics such as power consumption and delay for each technology node.

The 6-transistor XOR gate design is a very compact solution for implementing the XOR function. The schematic diagram is shown in Figure 1. The main drawback is the use of pass transistors which may create non-ideal logic levels due to threshold voltage degradation.

Six-transistor XOR gate. This paper proposes a design methodology for a digital library of cells resistant to cosmic radiation. Most important effects due to radiation are avoided or...

2019年5月1日 · In this paper, a new design of 6T XOR circuits based on Carbon Nanotube Field Effect Transistor (CNTFET) technology in 32 nm technology length is proposed for evaluation. They are simulated using...

The XOR gate is a fundamental component in digital electronics which are crucial for constructing binary adders, enabling arithmetic operations in computers. Proposed study presents the design and comparative analysis of a 6 T XOR gate implemented in 45 nm, 90 nm, and 180 nm CMOS technologies using Cadence tools.

Thereby, employed a proposed design comprising of 6T-XOR-cell, 1-bit Hybrid Full adder (HFA) design are implemented in a parallel prefix adder (PPA) which can be operated at a high speed computational environment such microprocessors, DSP-processors.

This paper proposes designing a 6T full adder using 2T XOR and 2T XNOR modules using Cadence Virtuoso GPDK 90nm technology. The 2T XOR and 2T XNOR modules will then be replaced with CPTL logic in the 6T full adder.

The proposed design of 6T XOR is given in Figure 4 and in Figure 3 Conventionally used 12T XOR gate is shown. In 6T XOR, basically two inverters and one pass transistor forms the logic of XOR gate.

2020年8月5日 · In this paper, a new design of 6T XOR circuits based on Carbon Nanotube Field Effect Transistor (CNTFET) technology in 32 nm technology length is proposed for evaluation. They are simulated using HSPICE, and the performance parameters such as average power, power dissipation voltage source, PDP and delay are determined.

2024年7月10日 · This study presents a new 16-bit KSA that utilizes an innovative 6T-Hybrid XOR-cell. The suggested design offers superior performance in terms of rapid operation and decreases the number of transistors by 50% opposed to the standard XOR-cell.