To solve this issue, we propose three techniques to achieve a 16Kb energy-efficient CSDB-eDRAM for cryogenic memory implementation. First, we propose a 4T CSDB-GC that is able to significantly improve the retention time. Second, we propose a wordline voltage off-chip tuning method to enhance the dual-port read speed and read-disturb free ...

This work introduces a dot-product processing macro using eDRAM array and explores its capability as an in-memory computing processing element. The proposed architecture implemented a pair of 2T eDRAM cells as a processing unit that can store and operate with ternary weights using only four transistors.

In this paper, we present a novel 4T GC-eDRAM bitcell that utilizes an internal feedback mechanism to significantly increase the data retention time in scaled CMOS technologies. A 2 kb memory macro was implemented in a low-power 65nm CMOS technology, displaying an over 3× improvement in retention time over the best previous publication at this ...

2023年6月2日 · GC eDRAM是一种6T SRAM和1T1C eDRAM折中选择的产物，它结合了SRAM (与数字CMOS技术兼容)和1T1C eDRAM (高存储密度)的优点，同时规避了SRAM (单元面积大)和1T1C eDRAM (破坏性读取、回写操作和需要特殊工艺步骤)的缺点。 但是，与SRAM相比，GC eDRAM的主要缺点仍然是其数据保持的动态特性，需要定期进行刷新操作。 最小的2T GC eDRAM电路如图3-18所示，由一个写晶体管 (QW)与一个读晶体管 (QR)组成，其中读晶体管 …

static, dual-port, boost-free eDRAM (CSDB-eDRAM) design in a commercial 40-nm CMOS process for operation at 4.2 K. Our contributions are as follows: 1) 4T CSDB-GC for high retention time: We present a 4T CSDB-GC design, which can significantly improve the retention time without any boost schemes but still

2021年3月4日 · 4t结构edram 4t结构edram ,eetop 创芯网论坛 (原名：电子顶级开发网)

2021年11月1日 · The 4T GC-eDRAM bitcell that utilizes an internal feedback mechanism to significantly increase the data retention time to 8.29 ms at 27 °C and 3.98 ms at 85 °C at 700 mV in scaled 65 nm CMOS technologies.

2017年7月7日 · This chapter proposed a 4T GC-eDRAM with internal feedback for use in scaled CMOS nodes characterized by high leakage currents. The bitcell design protects the weak data level (“0”) by a conditional, cell-internal feedback path, while the feedback does not protect the strong data level (“1”).

Abstract: Gain-cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded memory implementation, supporting low supply voltages. However, due to its structure, the readout scheme is slow and requires a high precision …

2020年8月10日 · Gain cell embedded DRAMs (GC-eDRAM) are a potential alternative for conventional static random access memories thanks to their attractive advantages such as high density, low-leakage, and two-ported operation. As CMOS technology nodes scale down, the design of GC-eDRAM at deeply scaled nanometer nodes becomes more challenging.