We demonstrate an ultra-wideband 32-GS/s SiGe track-and-hold amplifier with 58-GHz bandwidth and a compact footprint due to the inductorless design. The circuit achieves a third harmonic distortion of -64 dBc to -29 dBc at 1.0-Vpp differential input voltage swing thanks to a linearized switched preamplifier and switched emitter follower stage.

2012年2月1日 · GLOBALFOUNDRIES 32 nm high-k metal gate technology, with SiGe channel for V T control of P-field effect transistor, is taken into production. This epitaxial channel material is being introduced into high volume manufacturing in …

2025年1月8日 · alias: 锗化硅,SiGe. 在SiGe 材料中随着Ge成分的增加，其禁带宽度从硅的1.17电子伏递减到锗的0.67电子伏，能带宽度的变化降低了材料的电阻率。用SiGe 材料制成的晶体管在射频领域（f T >50 GHz)显示了极强的竞争优势。

Realized in a SiGe-BiCMOS process, and operating at 1.5 V supply voltage, the doubler achieves state-of-the-art conversion gain (6 dB), ${P_{\mathrm{ sat}}}$ (5.7 dBm) and efficiency (17%). The operation bandwidth, of more than one octave (14–32 GHz), demonstrates a remarkable improvement against previous works.

2012年2月1日 · GLOBALFOUNDRIES 32nm high-k metal gate technology, with SiGe channel for VT control of P-field effect transistor, is taken into production. This epitaxial channel material is being introduced...

Abstract: Two-step recessed SiGe-S/D pMOSFET [1] has been optimized with a combination of compressive stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally.

In this paper, we present the design and implementation of an ultra-high-speed (up to 32 GS/s) comparator suitable for either oversampled or Nyquist ADCs with medium resolution (5.0 to 7.9 bits). The comparator employs a preamplifier and master-slave (M/S) latches [1].

2012年3月1日 · The effect of a silicon germanium (SiGe) channel on pFET threshold voltage (V TH) mismatch in 32 nm high-K/metal-gate (HKMG) process is characterised. Additional variability is observed in the SiGe-channel pFET as compared with the …

摘要 GLOBALFOUNDRIES 32 nm 高k 金属栅技术，采用SiGe 沟道用于P 场效应晶体管的VT 控制，已投入生产。 这种外延沟道材料正被引入互补金属氧化物半导体技术的大批量制造中。 窄宽度晶体管的 SiGe 沟道 (cSiGe) 的形态受到工艺条件的仔细控制，例如外延生长温度、预烘烤条件或外延沉积前的原位 Si 凹槽。 在外延沉积之前，硅的原位凹槽消除了在 28 nm 技术中观察到的微负载效应。 由于此工艺步骤的成本很高，外延批处理系统已被评估以显着降低拥有成本。 从最 …

2007年11月1日 · In this paper, we propose two-step recessed SiGe-S/D structure to realize 32 nm node HP pMOSFET. The new structure and the optimization method are presented focusing on 20 nm gate length pMOSFETs. And the guideline for scaling of this structure down to 15 nm node generation will be discussed.