2020年12月15日 · This paper offers a reliable 10T SRAM topology capable of executing read/write operations with less power dissipation over certain range of frequencies. The results of the proposed cell are indicative of fine stability tuning along with smaller power consumption and moderate delay.

2022年1月12日 · Abstract: This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor.

This article proposes a high-speed and low-power 10T compute-static random-access memory (CSRAM) capable of conducting rowwise search operations and executing in-memory logic functions efficiently. A self-suppressed discharge scheme is implemented to curtail the power consumption of the search operation by reducing the discharge swing of the ...

2016年9月19日 · Objective: In this paper, a 10-T (Transistor) static random access memory (SRAM) cell with reduced power and with improved static noise margin (SNM) is proposed. The 10-T SRAM employs a single bitline with dynamic feedback control which enhances the …

This workshop presents a basic overview of different SRAM Cell Designs using LTSpice and ASU's Arizona State Predictive PDK (ASAP) 14nm FinFET node, using an intuitive approach to designing a simple SRAM Cells. This workshop also provides deep insights into recent advancements and current research trends in Memory Cell Designs.

2020年12月15日 · The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T...

2023年10月19日 · This paper introduces an SRAM cell with ten carbon nanotube field effect transistors (CNTFETs) named 10 T CNTFET SRAM cell to help with that and to address the drawback of most SRAM cells caused by their poor stability during read operation.

Thispaper examines and analyses a 10T SRAM (static randomaccess memory) cell, as well as comparing it to a normal 6T SRAM.

In this project analyzed 10T cell topologies of SRAM. All the cells have been designed and implemented using Cadence software (crack version). Their respective delays and power consumption have been calculated in GPDK 90 nm technology.

2022年5月27日 · This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor.