AMD K6 - Wikipedia
The AMD K6 architecture. The AMD K6 is a superscalar P5 Pentium-class microprocessor, manufactured by AMD, which superseded the K5. The AMD K6 is based on the Nx686 microprocessor that NexGen was designing when it was acquired by AMD.
List of AMD CPU microarchitectures - Wikipedia
AMD K6 – the K6 was not based on the K5 and was instead based on the Nx686 processor that was being designed by NexGen when that company was bought by AMD. The K6 was generally pin-compatible with the Intel Pentium (unlike NexGen's existing processors).
AMD K6 - 维基百科，自由的百科全书
K6处理器是AMD最后一代采用AMD完全兼容架构的处理器（K7换用了ALPHA架构EV6总线），其整数运算性能已经接近甚至超过了当时的对手Pentium和PentiumMMX，但浮点运算性能只有同频率Pentium处理器的1/2左右 [來源請求] 。
AMD K6 - 维基百科，自由的百科全书 - zh.wikipedia.org
K6处理器是AMD最后一代采用AMD完全兼容架构的处理器（K7换用了ALPHA架构EV6总线），其整数运算性能已经接近甚至超过了当时的对手Pentium和PentiumMMX，但浮点运算性能只有同频率Pentium处理器的1/2左右 [来源请求] 。
The AMD-K6 processor's RISC86 microarchitecture features a decoupled decode/execution superscalar design that provides enhanced sixth-generation performance and full x86 binary software compatibility.
AMD CPU微架構列表 - 维基百科，自由的百科全书
AMD Bulldozer - 是继 K10 之后，使用 AMD M-SPACE 模块化设计方法（modular design methodology）的下一代微架構。Bulldozer是为功耗在10W至100W类别的处理器而设计，应用XOP和FMA指令集，并且能结合GPU核心（AMD APU）。 AMD Piledriver - 第二代AMD 15h微架構。 AMD Steamroller - 第三代AMD 15h ...
AMD-K6 TM Processor Microarchitecture Overview and Product Update Lance L. Smith Director, Technical Marketing
AMD K6 266 MHz - AMD-K6/266AFR - CPU世界
2024年7月1日 · AMD K6 266 MHz desktop CPU: detailed specifications, benchmarks, side by side comparison, pictures and more from CPU-World
AMD K6 - CPU MUSEUM - MUSEUM OF MICROPROCESSORS
The K6 microprocessor was launched by AMD in 1997. The main advantage of this particular microprocessor is that it was designed to fit into existing desktop designs for Pentium branded CPUs. It was marketed as a product which could perform as well as its Intel Pentium II equivalent but at a significantly lower price.
AMD K6 - Pctechguide.com
Using AMD’s RISC86 superscalar microarchitecture, the chip decoded each x86 instruction into a series of simpler operations that could then be processed using typical RISC principles – such as out-of-order execution, register renaming, branch …