The controller exposes a native Tx/Rx user interface for CXL.io traffic as well as an Intel CXL-cache/mem Protocol Interface (CPI) for CXL.mem and CXL.cache traffic. There is also an CXL 2.0 ...

2.0 Design IP and successful completion of CXL 1.1 validation with Intel’s CXL host platform. Mobiveil’s CXL controller IP (COMPEX™) is a highly configurable, low-latency CXL controller that supports ...

XConn Technologies has unveiled its Apollo 2 hybrid switch, integrating both Compute Express Link (CXL) 3.1 and PCIe Gen 6.2 on a single chip.

V, MOS 6502 ... Intel's newly appointed CEO Lip-Bu Tan has used his first major speech to admit the x86 goliath needs to ...

A technical paper titled “Pond: CXL-Based Memory Pooling Systems for Cloud Platforms” was published by researchers at Virginia Tech, Intel, Microsoft Azure, Google, and Stone Co. “Public cloud ...

up to 96 PCIe 5.0 or CXL 2.0 lanes and six UPI 2.0 links with up to 24 gigatransfers per second. Intel will then release a few more categories of Xeon 6 processors in the first quarter of next year.

Astera was an early tester of CXL along with Intel Corp. CXL works with the current PCIe Gen 5 as a new open interconnect standard that targets intensive CPU workloads. And it’s quickly becoming ...

SMART Modular's NV-CMM, utilizing the CXL standard, combines the speed of DRAM with the persistence of NAND flash memory to deliver unprecedented performance and reliability for data-intensive ...